Recently non-volatile SRAM memory cell, in which a plurality of non-volatile memory sections are connected in parallel to SRAM, has been known (see Patent document 1, for example). As illustrated in FIG. 13, a conventional non-volatile SRAM memory cell 100 comprises an SRAM 2, a plurality of non-volatile memory sections 104a, 104b, and 104c. Each of the non-volatile memory sections 104a, 104b, and 104c is connected to each of a first storage node SNT and a second storage node SNB of the SRAM 2.
The SRAM 2 is composed of six MOS transistors, namely, first and second access transistors 6a and 6b, each composed of an N-type MOS (Metal-Oxide-Semiconductor) transistor, first and second load transistors 7a and 7b, each composed of a P-type MOS transistor, and first and second drive transistors 8a and 8b, each composed of an N-type MOS transistor.
In the SRAM 2, one end of the first load transistor 7a is connected to one end of the first drive transistor 8a. The SRAM 2 has the first storage node SNT between the first load transistor 7a and the first drive transistor 8a, which are connected in series. In the SRAM 2, one end of the second load transistor 7b is connected to one end of the second drive transistor 8b. The SRAM 2 has the second storage node SNB between the second load transistor 7b and the second drive transistor 8b, which are connected in series. The other end of each of the first load transistor 7a and the second load transistor 7b is connected to a power line VSp. The other end of each of the first drive transistor 8a and the second drive transistor 8b is connected to a reference voltage line VSn.
One end of the first access transistor 6a is connected to the first storage node SNT and a gate of each of the second load transistor 7b and the second drive transistor 8b, and the other end of the first access transistor 6a is connected to a first bit line BLT1. One end of the second access transistor 6b is connected to the second storage node SNB and a gate of each of the first load transistor 7a and the first drive transistor 8a, and the other end of the second access transistor 6b is connected to a second bit line BLB1. Each gate of the first access transistor 6a and the second access transistor 6b is connected to a common word line WL. Each of the first access transistor 6a and the second access transistor 6b turns on or off in accordance with a voltage difference between the word line WL and the first bit line BLT1 or the second bit line BLB1.
External data is written into the SRAM 2 by an external data writing operation, in which a high (-level) potential or a low (-level) potential corresponding to the external data is applied to the first storage node SNT and the second storage node SNB. Thereby the external data is stored as SRAM data in the first storage node SNT and the second storage node SNB.
The non-volatile memory section 104a comprising a pair of a first memory cell M100a and a second memory cell M100b, the non-volatile memory section 104b comprising a pair of a first memory cell M200a and a second memory cell M200b, and the non-volatile memory section 104c comprising a pair of a first memory cell M300a and a second memory cell M300b. The non-volatile memory sections 104a, 104b, 104c are connected in parallel to the SRAM 2. The non-volatile memory sections 104a, 104b, and 104c have the same configuration. Each of the non-volatile memory section 104a (the pair of the first and second memory cells M100a and M100b), the non-volatile memory section 104b (the pair of the first and second memory cells M200a and M200b), and the non-volatile memory section 104c (the pair of the first and second memory cells M300a and M300b) is a complementary-type cell of 2 cells/bit (two cells per bit).
The first memory cells M100a, M200a, and M300a and the second memory cells M100b, M200b, and M300b in the non-volatile memory sections 104a, 104b, and 104c have the same configuration. Hereinafter, the non-volatile memory section 104a in a first row will be described below. In the first memory cell M100a, one end of a first switch transistor 107a is connected to one end of a first resistive random access memory (first ReRAM) RT1. The first switch transistor 107a and the first ReRAM RT1 are connected in series. In the second memory cell M100b, one end of the second switch transistor 107b is connected to one end of a second resistive random access memory (second ReRAM) RB1. The second switch transistor 107b and the second ReRAM RB1 are connected in series.
Each of the first ReRAM (RT1, RT2, and RT3) and the second ReRAM (RB1, RB2, and RB3) is a memory comprising metal oxide, in which a resistance changes when a voltage is applied thereto, and a change in a resistance value is stored therein as data of “1” or “0”. In the non-volatile memory section 104a in the first row, the other end of the first ReRAM RT1 in the first memory cell M100a is connected to the other end of the second ReRAM RB1 in the second memory cell M100b. The other ends of the first ReRAM RT1 and the second ReRAM RB1 are connected to a common memory source line MS1. In another row, the other end of the first ReRAM (RT2, RT3) in the first memory cell (M200a, M300a) is connected to the other end of the second ReRAM (RB2, RB3) in the second memory cell (M200b, M300b). The other end of the first ReRAM (RT2, RT3) and the other end of the second ReRAM (RB2, RB3) are connected to a common memory source line (MS2, MS3).
In each of the first memory cell M100a and the second memory cell M100b, a common switch gate line CG1 is connected to the first switch transistor 107a and the second switch transistor 107b. Through one switch gate line CG1, the same voltage is applied to each gate of the first switch transistor 107a and the second switch transistor 107b. Similarly, in a memory cell (M200a, M300a) in another row, a common switch gate line (CG2, CG3) is connected to a first switch transistor (108a, 109a) and a second switch transistor (108b, 109b). Through one switch gate line (CG2, CG3), a common voltage is applied to each gate of the first switch transistor (108a, 109a) and the second switch transistor (108b, 109b) in the same row.
In a case where SRAM data stored in the SRAM 2 is programmed into the first memory cell M100a and the second memory cell M100b in the non-volatile memory section 104a in the first row of the non-volatile SRAM memory cell 100, the voltage Vdd is applied to the switch gate line CG1 in the first row and 0 V is applied to the switch gate lines CG2 and CG3 in the subsequent rows. Thereby, in the non-volatile memory section 104a in the first row, the first and second switch transistors 107a and 107b, which are connected to the switch gate line CG1, are turned on. The first storage node SNT in the SRAM 2 is electrically connected to the first ReRAM RT1 through the first switch transistor 107a. The second storage node SNB is electrically connected to the second ReRAM RB1 through the second switch transistor 107b. Thus the complementary SRAM data is programmed into the first memory cell M100a and the second memory cell M100b. 